FIG. 11 shows a schematic structure of a Super Twisted Nematic (STN) liquid crystal apparatus. As shown in the figure, the liquid crystal display apparatus includes a liquid crystal display panel 51, a segment driver 52, and a common driver 53. Although not shown, a plurality of scanning lines and signal lines are formed in the liquid crystal display panel 51. The segment driver 52 and the common driver 53 are drive circuits for supplying various signals (to be described later) to the liquid crystal display panel 51.
To the segment driver 52, a display data signal DATA and an input data shift clock XCK are respectively inputted via a buffer 54. To the common driver 53, a scanning start signal YD is inputted via the buffer 54. Further, an input data latch signal LP is inputted to the segment driver 52 and the common driver 53 via the buffer 54. A display control signal DISP is inputted via the buffer 54 to an alternating signal generating circuit 55 and a power sequence circuit 56.
The alternating signal generating circuit 55 generates an alternating signal M based on the display control signal DISP to be inputted thereto. The alternating signal M is inputted to the segment driver 52 and the common driver 53. The power sequence circuit 56 controls ON/OFF of the liquid crystal display panel 51 based on the display control signal DISP to be inputted thereto. The display control signal DISP outputted from the power sequence circuit 56 is respectively inputted to the segment driver 52, the common driver 53 and a DC/DC converter 57.
Other than the display control signal DISP, a logic source voltage V.sub.dd, and a contrast adjusting voltage V.sub.CON are inputted to the DC/DC converter 57. Then, the DC/DC converter 57 outputs a bias reference voltage V.sub.ee to the bias voltage generating circuit 58. The bias voltage generating circuit 58 outputs bias voltages (intermediate voltage) V.sub.1, V.sub.2, . . . , V.sub.n based on the bias reference voltage V.sub.ee to the segment driver 52 and the common driver 53.
Namely, in the described liquid crystal display apparatus, various signals, clocks and bias voltages V.sub.1, V.sub.2, . . . V.sub.n are inputted to the segment driver 52 and the common driver 53. As a result, a scanning line of the liquid crystal display panel 51 is selected as desired, and a predetermined dot of the liquid crystal display panel 51 is lightened in response to the display data signal DATA.
In the described liquid crystal display apparatus, even when the power of the apparatus is set in the OFF state, or a display is prohibited, a DC voltage is still being applied to the liquid crystal display panel 51. This causes degradation of the liquid crystal display panel 51 in its quality and appearance. In order to prevent such problem, it is required to remove charges stored on the liquid crystal display panel 51 when the power of the apparatus is set in the OFF state, or a display is prohibited.
For the described purpose, the conventional liquid crystal display apparatus includes a discharge circuit 59 to remove charges stored on the liquid crystal display panel 51 when the power of the apparatus is set in the OFF state or a display is prohibited.
As shown in FIG. 12, the discharge circuit 59 is formed by discharge resistors R.sub.1, R.sub.2, . . . R.sub.n. These discharge resistors R.sub.1, R.sub.2, . . . , R.sub.n are provided in parallel across respective bias voltages V.sub.1, V.sub.2, . . . V.sub.n, outputted from the bias voltage generating circuit 58, and a V.sub.ss line (0 V). In the described arrangement, when the power of the apparatus is set in the OFF state, or a display is prohibited, charges on the liquid crystal display panel 51 are removed via the discharge resistors R.sub.1, R.sub.2, . . . , R.sub.n by discharge.
On the other hand, FIG. 13 shows a schematic structure of the liquid crystal display apparatus which is disclosed, for example, by Japanese Unexamined Patent Application No. 46687/1984 (Tokukaisho 59-46687). In this liquid crystal display apparatus, a bias supply circuit 61 is connected to the V.sub.ss line (0V) via switching elements such as field effect transistors Q.sub.1 ' and Q.sub.2 '. When an application of bias voltages is not needed such as in a display prohibit drive mode, etc., the field effect transistors Q.sub.1 ' and Q.sub.2 ' are set in the OFF state.
According to the described arrangement, when the application of the bias voltages is not needed, the field effect transistors Q.sub.1 ' and Q.sub.2 ' are set in the OFF state. Therefore, a current does not flow in the V.sub.ss line via bias voltage generation-use voltage dividing resistors R.sub.1 ' and R.sub.2 '. As a result, a waste power consumption in the bias voltage generation-use voltage dividing resistors R.sub.1 ' and R.sub.2 ' when an application of bias voltages is not needed can be avoided.
However, in the arrangement of the conventional liquid crystal display apparatus shown in FIG. 12, as bias voltages V.sub.1, V.sub.2, . . . , V.sub.n are always applied to the liquid crystal display panel 51 and peripheral circuits, while the bias voltages V.sub.2, V.sub.2, . . . , V.sub.n are being applied thereto, a current from the bias voltage generating circuit 58 flows also in the discharge resistors R.sub.1, R.sub.2, . . . R.sub.n that are respectively connected to the bias voltages V.sub.1, V.sub.2, . . . , V.sub.n in parallel. Therefore, in the conventional arrangement, when the power of the apparatus is set in the ON state, a power P.sub.R is wasted.
For example, a waste power consumption in the case of generating four bias voltages V.sub.1, V.sub.2, V.sub.3 and V.sub.4 as shown in FIG. 14 will be considered. Generally, the power P.sub.R to be consumed in the discharge resistors R.sub.1, R.sub.2, . . . R.sub.n are given by the following equation: ##EQU1##
Assumed that the bias reference voltage V.sub.ee =30 V, then respective bias voltages V.sub.1, V.sub.2, V.sub.3 and V.sub.4 are respectively 28.125 V, 26.26 V, 3.75 V and 1.875 V, and the discharge resistors R.sub.1, R.sub.2, R.sub.3 and R.sub.4 are respectively 33 k.OMEGA.. From the above equation, the power P.sub.R to be consumed in the discharge resistors R.sub.1, R.sub.2, R.sub.3 and R.sub.4 is given as P.sub.R =45.4 mW. Here, these numeral values correspond to around 5 to 6 percents of the power consumed when displaying an image. Therefore, while the bias voltages V.sub.1, V.sub.2, V.sub.3 and V.sub.4 are being applied, the power P.sub.R is always consumed in the discharge circuit 59.
According to the arrangement of the described Japanese publication shown in FIG. 13, when the power of the apparatus is set in the OFF state, the power to be consumed in the bias supply circuit 61 can be saved by setting the field effect transistors Q.sub.1 ' and Q.sub.2 ' in the OFF state. However, when the field effect transistors Q.sub.1 ' and Q.sub.2 ' are set in the OFF state, charges stored on the liquid crystal display panel 62 do not flow in the V.sub.ss line (0 V) via the field effect transistors Q.sub.1 ' and Q.sub.2 '. As a result, the charges stored on the liquid crystal display panel 62 are not removed, which results in degradation of the liquid crystal display panel 62 in its quality and appearance.